Adaptive RAKE receiver structures for ultra wide-band systems

Ultra wide band (UWB) is an emerging technology that recently has gained regulatory approval. It is a suitable solution for high speed indoor wireless communications due to its promising ability to provide high data rate at low cost and low power consumption. Another benefit of UWB is its ability to...

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Bibliographic Details
Main Author: Wan, Quan
Other Authors: Waskowic, Peter
Format: Others
Language:en
Published: University of Saskatchewan 2006
Subjects:
UWB
Online Access:http://library.usask.ca/theses/available/etd-12302005-133729/
Description
Summary:Ultra wide band (UWB) is an emerging technology that recently has gained regulatory approval. It is a suitable solution for high speed indoor wireless communications due to its promising ability to provide high data rate at low cost and low power consumption. Another benefit of UWB is its ability to resolve individual multi-path components. This feature motivates the use of RAKE multi-path combining techniques to provide diversity and to capture as much energy as possible from the received signal. Potential future and rule limitation of UWB, lead to two important characteristics of the technology: high bit rate and low emitting power. Based on the power emission limit of UWB, the only choice for implementation is the low level modulation technology. To obtain such a high bit rate using low level modulation techniques, significant inter-symbol interference (ISI) is unavoidable. </p>Three N (N means the numbers of fingers) fingers RAKE receiver structures are proposed: the N-selective maximal ratio combiner (MRC), the N-selective MRC receiver with least-mean-square (LMS) adaptive equalizer and the N-selective MRC receiver with LMS adaptive combiner. These three receiver structures were all simulated for N=8, 16 and 32. Simulation results indicate that ISI is effectively suppressed. The 16-selective MRC RAKE receiver with LMS adaptive combiner demonstrates a good balance between performance, computation complexity and required length of the training sequence. Due to the simplicity of the algorithm and a reasonable sampling rate, this structure is feasible for practical VLSI implementations.