| Summary: | A group of new non-volatile memory technologies with characteristics making them worthy of consideration for different parts of the memory hierarchy, including the main memory, are emerging. In this thesis I discuss the state of STT-RAM, ReRAM and PCM technologies which are three of the front runners in this group of new technologies. I also simulate the performance of PCM used as main memory using Intel’s binary instrumentation framework Pin and compare it to DRAM to explore three research questions. Firstly, in the case of horizontally integrated PCM and DRAM I test a data mapping policy where an application’s stack is mapped to DRAM and the heap is mapped to PCM. I find that in the case of my simulation this mapping have no benefits since most of the stack is continually kept in the cache which causes the DRAM to end up unutilized. Secondly, I compare the read latency between PCM and DRAM and find an average increase 48 %for PCM. Thirdly, I compare the energy costs of two write policiesfor PCM. The first being write-through of dirty bytes at byte granularity and the second being full row buffer write-back. I find that the first method has on average less than a third of the energy cost compared to the second method.T
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