Verification of Software under Relaxed Memory

The work covered in this thesis concerns automatic analysis of correctness of parallel programs running under relaxed memory models. When a parallel program is compiled and executed on a modern architecture, various optimizations may cause it to behave in unexpected ways. In particular, accesses to...

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Main Author: Leonardsson, Carl
Format: Doctoral Thesis
Language:English
Published: Uppsala universitet, Avdelningen för datorteknik 2016
Subjects:
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-297201
http://nbn-resolving.de/urn:isbn:978-91-554-9616-6
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spelling ndltd-UPSALLA1-oai-DiVA.org-uu-2972012016-08-25T05:09:36ZVerification of Software under Relaxed MemoryengLeonardsson, CarlUppsala universitet, Avdelningen för datorteknikUppsala universitet, DatorteknikUppsala2016verificationrelaxed memory modelsThe work covered in this thesis concerns automatic analysis of correctness of parallel programs running under relaxed memory models. When a parallel program is compiled and executed on a modern architecture, various optimizations may cause it to behave in unexpected ways. In particular, accesses to the shared memory may appear in the execution in the opposite order to how they appear in the control flow of the original program source code. The memory model determines which memory accesses can be reordered in a program on a given system. Any memory model that allows some observable memory access reordering is called a relaxed memory model. The reorderings may cause bugs and make the production of parallel programs more difficult. In this work, we consider three main approaches to analysis of correctness of programs running under relaxed memory models. An exact analysis for finite state programs running under the TSO memory model (Paper I). This technique is based on the well quasi ordering framework. An over-approximate analysis for integer programs running under TSO (Paper II), based on predicate abstraction combined with a buffer abstraction. Two under-approximate analysis techniques for programs running under the TSO, PSO or POWER memory models (Papers III and IV). The latter two techniques are based on stateless model checking and dynamic partial order reduction. In addition to determining whether a program is correct under a given memory model, the problem of automatic fence synthesis is also considered. A memory fence is an instruction that can be inserted into a program in order to locally disable some memory access reorderings. The fence synthesis problem is the problem of automatically inferring a minimal set of memory fences which restores sufficient order in a given program to ensure its correctness. UPMARCDoctoral thesis, comprehensive summaryinfo:eu-repo/semantics/doctoralThesistexthttp://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-297201urn:isbn:978-91-554-9616-6Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, 1651-6214 ; 1387application/pdfinfo:eu-repo/semantics/openAccess
collection NDLTD
language English
format Doctoral Thesis
sources NDLTD
topic verification
relaxed memory models
spellingShingle verification
relaxed memory models
Leonardsson, Carl
Verification of Software under Relaxed Memory
description The work covered in this thesis concerns automatic analysis of correctness of parallel programs running under relaxed memory models. When a parallel program is compiled and executed on a modern architecture, various optimizations may cause it to behave in unexpected ways. In particular, accesses to the shared memory may appear in the execution in the opposite order to how they appear in the control flow of the original program source code. The memory model determines which memory accesses can be reordered in a program on a given system. Any memory model that allows some observable memory access reordering is called a relaxed memory model. The reorderings may cause bugs and make the production of parallel programs more difficult. In this work, we consider three main approaches to analysis of correctness of programs running under relaxed memory models. An exact analysis for finite state programs running under the TSO memory model (Paper I). This technique is based on the well quasi ordering framework. An over-approximate analysis for integer programs running under TSO (Paper II), based on predicate abstraction combined with a buffer abstraction. Two under-approximate analysis techniques for programs running under the TSO, PSO or POWER memory models (Papers III and IV). The latter two techniques are based on stateless model checking and dynamic partial order reduction. In addition to determining whether a program is correct under a given memory model, the problem of automatic fence synthesis is also considered. A memory fence is an instruction that can be inserted into a program in order to locally disable some memory access reorderings. The fence synthesis problem is the problem of automatically inferring a minimal set of memory fences which restores sufficient order in a given program to ensure its correctness. === UPMARC
author Leonardsson, Carl
author_facet Leonardsson, Carl
author_sort Leonardsson, Carl
title Verification of Software under Relaxed Memory
title_short Verification of Software under Relaxed Memory
title_full Verification of Software under Relaxed Memory
title_fullStr Verification of Software under Relaxed Memory
title_full_unstemmed Verification of Software under Relaxed Memory
title_sort verification of software under relaxed memory
publisher Uppsala universitet, Avdelningen för datorteknik
publishDate 2016
url http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-297201
http://nbn-resolving.de/urn:isbn:978-91-554-9616-6
work_keys_str_mv AT leonardssoncarl verificationofsoftwareunderrelaxedmemory
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