Automatic Verification of Microprocessor designs using Random Simulation
Verification of microprocessor cores has always been a major challenge and a crucial phase in the development of a microprocessor. Increasing chip complexities and decreasing time-to-market windows has led to steady increase in the verification costs. Automatic verification of microprocessor desi...
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| Format: | Others |
| Language: | English |
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Uppsala universitet, Institutionen för informationsteknologi
2012
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-179273 |
| Summary: | Verification of microprocessor cores has always been a major challenge and a crucial phase in the development of a microprocessor. Increasing chip complexities and decreasing time-to-market windows has led to steady increase in the verification costs. Automatic verification of microprocessor designs based on random simulation helps to quickly capture inconceivable corner cases that would not have been found by manual testing. This thesis work focuses on the design and implementation of a Co-Simulation testbench platform together with a framework for generating random assembly programs for the functional verification of the OpenRISC Processor, OR1200. A Random Program Generator based on configurable instruction weights is developed to generate large test volumes. These random test programs are used to verify the functional correctness of the Register Transfer Logic model of a processor against a behavioral Instruction Set C Simulator. The simulation results show the effectiveness of this approach. Histograms are used to graphically illustrate the instruction and register coverage statistics. |
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