Efficient Ray Tracing of Sparse Voxel Octrees on an FPGA
Ray tracing of sparse voxel octrees is a method of rendering images of 3D models, which could soon become practical for use in real time applications. This is desirable as ray tracing can produce very realistic visualizations, while voxel models can represent models with very fine geometric detail....
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Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon
2012
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ndltd-UPSALLA1-oai-DiVA.org-ntnu-194152013-01-08T13:45:18ZEfficient Ray Tracing of Sparse Voxel Octrees on an FPGAengWilhelmsen, AudunNorges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjonInstitutt for elektronikk og telekommunikasjon2012ntnudaim:8130MTEL elektronikkDesign av digitale systemerRay tracing of sparse voxel octrees is a method of rendering images of 3D models, which could soon become practical for use in real time applications. This is desirable as ray tracing can produce very realistic visualizations, while voxel models can represent models with very fine geometric detail. For these reason the method has attracted significant attention in recent years, but no hardware solution has been published yet. This thesis presents a design of ray tracing of sparse voxel octrees in hardware. The objective is to show if it is sensible to implement the method in hardware, and if it could be integrated on modern GPUs alongside rasterization. To this end, the techniques used in existing software implementations of this method is reviewed, and an algorithm suitable for hardware implementation is presented. The problems of integrating the method with rasterization is explored, and the algorithm is analyzed and optimized to improve efficiency in hardware. A software implementation is presented, which supports the development of a hardware design. This design is implemented using the Verilog hardware description language, and it has been simulated and synthesized for an FPGA prototype. Multiple versions of the design has been synthesized and tested, and to evaluate the impact of design parameters the test results from these designs is presented. The thesis provides a comprehensive evaluation of the proposed design, and the results indicate that the algorithm is well suited for hardware implementation. Although real-time performance was not achieved, there are indications that further optimizations should allow real-time performance on the same platform, and that a full scale implementation on a modern GPU could probably allow ray tracing with a quality which is competitive with rasterization. Student thesisinfo:eu-repo/semantics/bachelorThesistexthttp://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-19415Local ntnudaim:8130application/pdfinfo:eu-repo/semantics/openAccess |
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English |
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ntnudaim:8130 MTEL elektronikk Design av digitale systemer |
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ntnudaim:8130 MTEL elektronikk Design av digitale systemer Wilhelmsen, Audun Efficient Ray Tracing of Sparse Voxel Octrees on an FPGA |
description |
Ray tracing of sparse voxel octrees is a method of rendering images of 3D models, which could soon become practical for use in real time applications. This is desirable as ray tracing can produce very realistic visualizations, while voxel models can represent models with very fine geometric detail. For these reason the method has attracted significant attention in recent years, but no hardware solution has been published yet. This thesis presents a design of ray tracing of sparse voxel octrees in hardware. The objective is to show if it is sensible to implement the method in hardware, and if it could be integrated on modern GPUs alongside rasterization. To this end, the techniques used in existing software implementations of this method is reviewed, and an algorithm suitable for hardware implementation is presented. The problems of integrating the method with rasterization is explored, and the algorithm is analyzed and optimized to improve efficiency in hardware. A software implementation is presented, which supports the development of a hardware design. This design is implemented using the Verilog hardware description language, and it has been simulated and synthesized for an FPGA prototype. Multiple versions of the design has been synthesized and tested, and to evaluate the impact of design parameters the test results from these designs is presented. The thesis provides a comprehensive evaluation of the proposed design, and the results indicate that the algorithm is well suited for hardware implementation. Although real-time performance was not achieved, there are indications that further optimizations should allow real-time performance on the same platform, and that a full scale implementation on a modern GPU could probably allow ray tracing with a quality which is competitive with rasterization. |
author |
Wilhelmsen, Audun |
author_facet |
Wilhelmsen, Audun |
author_sort |
Wilhelmsen, Audun |
title |
Efficient Ray Tracing of Sparse Voxel Octrees on an FPGA |
title_short |
Efficient Ray Tracing of Sparse Voxel Octrees on an FPGA |
title_full |
Efficient Ray Tracing of Sparse Voxel Octrees on an FPGA |
title_fullStr |
Efficient Ray Tracing of Sparse Voxel Octrees on an FPGA |
title_full_unstemmed |
Efficient Ray Tracing of Sparse Voxel Octrees on an FPGA |
title_sort |
efficient ray tracing of sparse voxel octrees on an fpga |
publisher |
Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon |
publishDate |
2012 |
url |
http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-19415 |
work_keys_str_mv |
AT wilhelmsenaudun efficientraytracingofsparsevoxeloctreesonanfpga |
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