Design and Simulation of Miscellaneous Blocks of an All-Digital PLL for the 60 GHz Band

• Main Authors: Butt, Hadiyah, Padala, Manjularani
• Format: Others
• Language: English
• Published: Linköpings universitet, Elektroniksystem 2013
• Subjects: ADPLL; PLL; DCO; TDC
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87158

A phase-locked loop commonly known as PLL is widely used in communication systems. A PLL is used in radio, telecommunications, modulation and demodulation. It can be used for clock generation, clock recovery from data signals, clock distribution and as a frequency synthesizer. Most electronic circuits encounter the problem of the clock skew. The clock Skew for a synchronous circuit is defined as the difference in the time of arrival between two sequentially adjacent registers. The registers and the flip-flops do not receive the clock at the same time. The clock signal in a normal circuit is generated with an oscillator, oscillator produces error, due to which there is a distortion from the expected time interval. The PLLs are used to address the problem. A phase-locked loop works to ensure the time interval seen at the clocks of various registers and the flip-flops match the time intervals generated by the oscillator. PLLs are trivial and an essential part of the micro-processors. Traditional PLLs are designed to work as an analog building block, but it is difficult to integrate them on a digital chip. Analog PLLs are less affected by noise and process variations. Digital PLLs allow faster lock time and are used for clock generation in high performance microprocessors. A digital PLL has more advantages as compared to an analog PLL. Digital PLLs are more flexible in terms of calibration, programability, stability and they are more immune to noise. The cost of a digital PLL is less as compared to its analog counter part. Digital PLLs are analogous to the analog PLLs, but the components used for implementing a digital PLL are digital. A digitally controlled oscillator (DCO) is utilized instead of a voltage controlled oscillator. A time to digital converter(TDC) is used instead of the phase frequency detector. The analog filter is replaced with a digital low pass filter. Phase-locked loop is a very good research topic in electronics. It covers many topics in the electrical systems such as communication theory, control systems and noise characterization. This project work describes the design and simulation of miscellaneous blocks of an all-digital PLL for the 60 GHz band. The reference frequency is 54 MHz and the DCO output frequency is 2 GHz to 3 GHz in a state-of the-art 65 nm process, with 1 V supply voltage. An all-digital PLL is composed of digital components such as a low pass filter, a sigma delta modulator and a fractional N /N +1 divider for low voltage and high speed operation. The all-digital PLL is implemented in MATLAB and then the filter, a sigma delta modulator and a fractional N /N +1 divider are implemented in MATLAB and Verilog-A code. The sub blocks i.e full adder, D flip-flop, a digital to digital converter, a main counter, a prescalar and a swallow counter are implemented in the transistor level using CMOS 65nm technology and functionality of each block is verified.