A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages.

• Main Author: Gundala, JayaKrishna
• Format: Others
• Language: English
• Published: Linköpings universitet, Elektroniksystem 2011
• Subjects: Oversampling ratio; Noise-shaping; Δ-Σ ADC; Filter Optimization; FIR filter; CIC filter; Decimation; TECHNOLOGY; TEKNIKVETENSKAP
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69319

The filter complexity in the multi-stage decimation system of a Δ-Σ ADC increases progressively as one moves to higher stages of decimation due to the fact that the input word length of the higher stages also increases progressively. The main motivation for this thesis comes from the idea of investigating a way, to reduce the input word length in the later filter stages of the decimation system which could reduce the filter complexity. To achieve this, we use a noise-shaping loop between the first and later stages so that the input word length for the later stages remains smaller than in the case where we do not use the noise-shaping loop. However, the performance (SNR/ Noise-level) level should remain the same in both cases. This thesis aims at analyzing the implications of using a noise-shaping loop in between the decimation stages of a Δ-Σ ADC and also finding the appropriate decimation filter types that could be used in such a decimation system. This thesis also tries to compare the complexity introduced by using the noise-shaping loop with the reduction achieved in the later decimation stages in terms of the input word length. Filter required in the system will also be optimized using minimax optimization technique.