TAM Design for Parallel Testing under Bus Bandwidth Limit
The complexity of electronic system is increasing rapidly and many of the electronic systems are embedded systems implemented as system-on-chip (SoC). This increasing complexity of SoC leads to longer test application time (TAT). One approach to reduce the TAT is to...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, ESLAB - Laboratoriet för inbyggda system
2010
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-62671 |