| Summary: | Today, the mobile communication systems can be found everywhere due to thelow cost and high degree integration level which is achievable with CMOS. Theuser can use a number of applications using only one device. The transmitteris one of the main blocks in communication systems for transmitting the signal,where the RF power a mplifier (PA) amplifies the RF signal to the r equiredoutput power so that signal can reach the r eceiver. Nowadays mostly transmitteremploys such modulation schemes which have high data rate and to amplify suchsignals, a linear PA is required. The efficiency of the PA should also be high, sothat it can provide high output power to load without consuming much poweritself.This thesis work describes the “CMOS Power Amplifier for IEEE 802.11g/nstandard (2.4GHz) in 65nm process”. The PA is a two stage amplifier biasedin Class AB mode with LC type input matching. The inter-stage matching iscarried out by the RF choke of the driver stage and the input capacitance of thepower stage. The output of the PA is power matched to the load. A linearizingtechnique is implemented to make PA more linear. The simulation results showsthat the designed PA gives 1dB compression point of +23.36dBm, a gain of26.82dB, a power added efficiency of 30%, a linear current of 122.30mA providing18dBm power to load and saturated output power of 24.45dBm.
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