Behavioral model of an address generation unit

• Main Author: Gustafsson, Henrik
• Format: Others
• Language: English
• Published: Linköpings universitet, Institutionen för systemteknik 2003
• Subjects: Electronics; VHDL; DSP; AGU; adress generation unit; modulo; Elektronik
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2106

This thesis is a part of a bigger project which goal is to make a DSP that is instruction compatible with the Motorola DSP56002. The goal of this part is to make a behavioural model with timing of the address generation unit in the DSP. The AGU unit can handle 4 different types of arithmetic’s including linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles several ways of calculating addresses as post/pre increment/decrement by a number. It can address 3 different memories, where 2 new addresses can be calculated at the same time in different memories. This model will be used as a golden model for the RTL model of the AGU that is one of the main parts in the DSP.