Comparative study on low-power high-performance flip-flops

• Main Author: Oskuii, Saeeid Tahmasbi
• Format: Others
• Language: English
• Published: Linköpings universitet, Institutionen för systemteknik 2004
• Subjects: Electronics; flip flops; latches; low power; standard cell; cell library; energy delay space; Elektronik
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2077

This thesis explores the energy-delay space of eight widely referred flip-flops in a 0.13µm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on the comparison results, transmission gate-based flip-flops show the best powerperformance trade-offs with a total delay (clock-to-output + setup time) down to 105ps. For higher performance, the pulse-triggered flip-flops are the fastest (80ps) alternatives suitable to be included in a flip-flop cell library. However, pulse-triggered flip-flops consume significantly larger power (about 2.5x) compared to other fast but fully dynamic flip-flops such as TSPC and dynamic TG-based flip-flops.