Design and Evaluation of an Ultra-Low Power Successive Approximation ADC

• Main Author: Zhang, Dai
• Format: Others
• Language: English
• Published: Linköpings universitet, Institutionen för systemteknik 2009
• Subjects: Analog-to-digital converter (ADC); charge redistribution; CMOS; low power; low supply voltage; successive approximation; latched comparator; Electrical engineering; Elektroteknik
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.