Design and Implementation of an Asynchronous Pipelined FFT Processor
FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K poi...
Main Author: | Claesson, Jonas |
---|---|
Format: | Others |
Language: | English |
Published: |
Linköpings universitet, Institutionen för systemteknik
2003
|
Subjects: | |
Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1812 |
Similar Items
-
Implementation of an FFT algorithm using a soft processor core
by: Gallay, Lucie
Published: (2002) -
Design and Evaluation of a Single Instruction Processor
by: Mu, Rongzeng
Published: (2003) -
A Parameterizable Standard Cell Generator
by: Ekebrand, Terese, et al.
Published: (2003) -
Improved implementation of a 1K FFT with low power consumption
by: Näslund, Petter, et al.
Published: (2005) -
Asynchronous Wrapper for Globally Asynchronous Locally Synchronous Systems
by: Manbo, Olof
Published: (2002)