Hardware Implementation of multiple encoding schemes during memory transfers

• Main Author: Sampayo, Garcia José Luis
• Format: Others
• Language: English
• Published: KTH, Skolan för informations- och kommunikationsteknik (ICT) 2012
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-98666

Todays demand for enhancing the user experience and high performance represents an increase of functionality of the systems involved. This translates into high scale of integration. With the continuing growth of high scale of integration come new challenges that lead to an increment of noise in the platform. This is true for devices ranging from high transaction servers to small mobile devices. Noise sources like crosstalk and inter-symbol interference, which affect the signal integrity, are caused by the high density interconnect combined with the increase of frequency of operation. This kind of noise sources are the cause of logic errors, false switching or even a system failure. In addition to the aforementioned problems, is that power consumption lately has become one of the main metrics for performance and also one of the main constraints due to the global concerns regarding CO 2emissions. Today there is concern to reduce it both in mobile and servers. In the case of servers to reduce cooling which reflects directly into the companies bill expenses and more importantly to adopt "green technologies" and in the case of mobile to extend the battery life. In particular high speed buses play an important role regarding power consumption and one of the main high speed buses namely the memory subsystem continues to be the bottleneck for high performance. The gap between the CPU (Control Processing Unit) executing an instruction and fetching a data from memory is very large. The use of memory hierarchy tries to compensate for this gap. Even so, the memory bandwidth is still limited by interconnection noise sources. DDR3 (Double Data Rate 3) is one of the main high interconnect protocol buses used in computer systems. This protocol already uses an encoding technique for error control coding (ECC). Also incorporates solutions to reduce power consumption and alleviate SI (Signal Integrity) issues, which limit the data rate, however extending its performance remains a challenge. Due to the aforementioned problems, researches are trying to bring new solutions that try to keep up with the CPU advances. Among the solutions are new techniques in the form of encoding schemes such that mitigate crosstalk and reduce power consumption. These proposals seem very promising in order to keep up with the data rate increase. It is of interest to evaluate multiple encoding schemes using one of the main high speed buses, namely DDR3, but currently there is not a single platform that allows the evaluation of several encoding schemes during memory transfers. A feasible solution is to emulate the memory system by the use of FPGA’s (Field Programmable Gate Array) and modify it to incorporate some encoding. The purpose of this thesis is to define and implement an architecture aimed at evaluation of multiple encoding schemes during memory transfers. Some of the use of these encoding schemes is aimed at reduce crosstalk and some at reduce power consumption and overall improve system performance.