Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging
This thesis describes the development of wafer-level fabrication and packaging methods for micro-electromechanical (MEMS) devices, based on wafer-bonding. The first part of the thesis is addressing the development of a wafer-level technology that allows the use of high performance materials, such as...
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| Format: | Doctoral Thesis |
| Language: | English |
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KTH, Mikro- och nanosystemteknik
2013
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-125913 http://nbn-resolving.de/urn:isbn:978-91-7501-843-0 |