Mapping to a Time-predictable Multiprocessor System-on-Chip

• Main Author: Amstutz, Christian
• Format: Others
• Language: English
• Published: KTH, Skolan för informations- och kommunikationsteknik (ICT) 2012
• Subjects: Mapping; Synchronous Systems; Multiprocessor System-on-Chip; Design Methodology; Time-predictability
• Online Access: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-121296

Traditional design methods could not cope with the recent development of multiprocessorsystems-on-chip (MPSoC). Especially, hard real-time systems that requiretime-predictability are cumbersome to develop. What is needed, is an efficient, automaticprocess that abstracts away all the implementation details. ForSyDe, a designmethodology developed at KTH, allows this on the system modelling side. The NoCSystem Generator, another project at KTH, has the ability to create automaticallycomplex systems-on-chip based on a network-on-chip on an FPGA. Both of themsupport the synchronous model of computation to ensure time-predictability. Inthis thesis, these two projects are analysed and modelled. Considering the characteristicsof the projects and exploiting the properties of the synchronous model ofcomputation, a mapping process to map processes to the processors at the differentnetwork nodes of the generated system-on-chip was developed. The mapping processis split into three steps: (1) Binding processes to processors, (2) Placement of theprocessors on net network nodes, and (3) scheduling of the processes on the nodes.An implementation of the mapping process is described and some synthetic exampleswere mapped to show the feasibility of algorithms.