Energy Efficiency of Computation in All-spin Logic: Projections and Fundamental Limits

• Main Author: Chen, Zongya
• Format: Others
• Published: ScholarWorks@UMass Amherst 2019
• Subjects: All-spin Logic; Spintronics; Energy Efficiency; Electrical and Electronics; Electronic Devices and Semiconductor Manufacturing; Power and Energy
• Online Access: https://scholarworks.umass.edu/masters_theses_2/754; https://scholarworks.umass.edu/cgi/viewcontent.cgi?article=1779&context=masters_theses_2

Built with nanomagnets, a spintronic device called the all-spin logic (ASL) device carries information with only spin currents, resulting in a low power supply--10 mV. This voltage is 100 times smaller than the conventional CMOS devices (usually 0.8~1V). The potential for improved energy efficiency made possible by the low operating voltage of ASL makes it one of the most promising devices among its post-CMOS competitors. The basic working principles of ASL device are introduced in this thesis and two complementary approaches to studying energy efficiency of computation are applied to a common set of ASL circuits: (1) a circuit simulation approach that provides efficiency estimates for specific ASL circuit realizations, and (2) a physical-information-theoretic approach that reveals fundamental efficiency bounds for ASL circuits as limited by irreversible information loss. The results of this study support the expectation that the energy efficiency of computation in ASL can far exceed that of CMOS. However, it also reveals that ASL efficiencies--shown to exceed fundamental limits by many orders of magnitude in the ASL implementations studied here--are unlikely to approach fundamental limits because of the unavoidable energetic overhead cost of maintaining spin currents.