| Summary: | Increasing complexity of ICs and system on chip (SOC) requires the development of advanced CAD tools that will raise the level of design abstraction from register transfer level (RTL) to algorithmic and behavioral levels. One of the tools needed for the designer is to do fast design space exploration, down to the physical level, without actually performing all pieces of the synthesis. In this work, a fast high level design estimation framework is presented, which includes the transformations from structural to architectural, to physical. This work, along with the functional-to-structural transformation framework, provides an infrastructure for an early design space exploration. The structural to architectural transformation includes the constrained problems involving the data flow graph (DFG) selection from the abstract data flow graph (ADFG), scheduling, allocation and binding. The maximum operation sharing rule is adopted in DFG selection algorithm. A satisfiability based functional unit binding is performed after the latency constrained minimum area scheduling. Then, a minimum register binding algorithm is presented. Finally, a variable swapping algorithm for minimizing the interconnect is proposed. The architectural synthesis flow is tackled in such a hierarchical approach and is proven to be very fast. A graph-based, rectangular dual floorplanning method is proposed for the architectural to physical transformation for a minimum area floorplan, given the constraints specified by the designers. The designers guide the construction of an adjacency graph for a properly triangulated graph (PTG), which provides a sufficient condition for a legal floorplan. In this work, the legal floorplan is constructed by decomposing from the PTG into a pair of dual digraphs. The floorplan is optimized for area by satisfying linear constraints imposed by the designers. The proposed floorplanning approach is proven extremely fast compared with the simulated annealing approaches. We also include a temperature-aware floorplanning application to demonstrate the power of the proposed floorplanning approach. Experimental results show that the proposed flow is very fast. The generated floorplans have reasonable quality in area. Also included in this work is the constrained yield enhancement problem in architectural synthesis level.
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