| Summary: | Recently demands for wireless data communication, especially high-speed, wireless local area networks (WLANS), are growing rapidly. In contrast to wireline data communication, radio frequency (RF) wireless channels have a physically limited bandwidth and error-prone communication medium. Hence the development of high-speed, cost-effective wireless LANs presents a greater challenge than wireline LANs. Real-time coding significantly enhances the network performance by improving both the effective bandwidth and the reliability of RF channels. Yet since it introduces additional hardware cost and operating power consumption as well as coding delay, any hardware coder needs to be small, low-power, reliable, and high-performance. The rapid advent of VLSI technology coupled with many advanced design tools allows computationally intensive coding algorithms to be efficiently implemented at low cost within a short design cycle. Therefore, dedicated special purpose hardware provides a cost-efficient and high-performance alternative to general purpose processors. This dissertation presents new novel computational structures for widely used source coding algorithms: (1) Lempel-Ziv compression for lossless data and (2) Pyramid Vector Quantization for compressing image data. To satisfy transparent and real-time coding requirements, we focus on the design of parallel algorithms and high-performance VLSI architectures while minimizing implementation costs including area, power and design costs. High-level estimations and trade-offs are performed by looking at parallelism and pipelining of the algorithms with the aid of regular array synthesis methods. Yet, as for many search based coding algorithms, these source coding algorithms belong to a new class of regular algorithms, mainly run-time data-dependent iteration loops. We develop an algorithmic transformation to convert data-dependent regular algorithms to data-independent regular algorithms so that well-known regular array synthesis methods (46) can be applied. Using our methodology, we systematically develop new parallel algorithms and VLSI architectures for these codings to be employed in wireless LANs. Analyzing the computational structures and deriving parallel algorithms not only allows us to exploit the inherent parallelism and regularity but also allows appropriate design choices depending on VLSI cost and performance requirements. To demonstrate the correctness of our design and methodologies, we have designed a prototype VLSI chip for our Lempel-Ziv data compression architecture. Finally, we study the impact of real-time VLSI data compression on the performance and the average power consumption of the proposed IEEE 802.11 wireless LAN standard.
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