Design and evaluation of a high performance multi-priority multicast ATM switch

Asynchronous Transfer Mode (ATM) is believed to be the standard protocol for the extremely demanding high speed networking field. The switching technologies employed in A TM cell switches are extensively researched and studied in recent years. However, most developed switches nowadays are lack of...

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Main Author: Lam, Patrick
Format: Others
Language:English
Published: 2009
Online Access:http://hdl.handle.net/2429/9663
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spelling ndltd-UBC-oai-circle.library.ubc.ca-2429-96632018-01-05T17:34:53Z Design and evaluation of a high performance multi-priority multicast ATM switch Lam, Patrick Asynchronous Transfer Mode (ATM) is believed to be the standard protocol for the extremely demanding high speed networking field. The switching technologies employed in A TM cell switches are extensively researched and studied in recent years. However, most developed switches nowadays are lack of either performance or costefficiency. Furthermore, most switching researches published are based on uniform incoming cell traffic pattern, which is very different from real time traffics. Real time traffics are not only bursty, they are also involved with multiple classes of prioritized traffics, as well as multicast traffic. In this thesis, a high performance and cost-effective A TM switch architecture is introduced. The switching architecture is based on two existing technologies, namely Skew Round Robin scheduling and Virtual Output Queuing schemes. These two schemes are proved to be simple and high performers under uniform traffic pattern [16]. Simulation results show that with a little modification made to these schemes, a switch can perform extremely well under many kinds of real time traffic patterns, including multi-priority and multicast. In addition, with the proposed switching architecture, it's shown that cell loss ratio can be arbitrarily reduced — with finite buffer size and bounded delay - even under bursty traffic pattern. Applied Science, Faculty of Electrical and Computer Engineering, Department of Graduate 2009-06-25T23:30:34Z 2009-06-25T23:30:34Z 1999 1999-11 Text Thesis/Dissertation http://hdl.handle.net/2429/9663 eng For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. 5544286 bytes application/pdf
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language English
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description Asynchronous Transfer Mode (ATM) is believed to be the standard protocol for the extremely demanding high speed networking field. The switching technologies employed in A TM cell switches are extensively researched and studied in recent years. However, most developed switches nowadays are lack of either performance or costefficiency. Furthermore, most switching researches published are based on uniform incoming cell traffic pattern, which is very different from real time traffics. Real time traffics are not only bursty, they are also involved with multiple classes of prioritized traffics, as well as multicast traffic. In this thesis, a high performance and cost-effective A TM switch architecture is introduced. The switching architecture is based on two existing technologies, namely Skew Round Robin scheduling and Virtual Output Queuing schemes. These two schemes are proved to be simple and high performers under uniform traffic pattern [16]. Simulation results show that with a little modification made to these schemes, a switch can perform extremely well under many kinds of real time traffic patterns, including multi-priority and multicast. In addition, with the proposed switching architecture, it's shown that cell loss ratio can be arbitrarily reduced — with finite buffer size and bounded delay - even under bursty traffic pattern. === Applied Science, Faculty of === Electrical and Computer Engineering, Department of === Graduate
author Lam, Patrick
spellingShingle Lam, Patrick
Design and evaluation of a high performance multi-priority multicast ATM switch
author_facet Lam, Patrick
author_sort Lam, Patrick
title Design and evaluation of a high performance multi-priority multicast ATM switch
title_short Design and evaluation of a high performance multi-priority multicast ATM switch
title_full Design and evaluation of a high performance multi-priority multicast ATM switch
title_fullStr Design and evaluation of a high performance multi-priority multicast ATM switch
title_full_unstemmed Design and evaluation of a high performance multi-priority multicast ATM switch
title_sort design and evaluation of a high performance multi-priority multicast atm switch
publishDate 2009
url http://hdl.handle.net/2429/9663
work_keys_str_mv AT lampatrick designandevaluationofahighperformancemultiprioritymulticastatmswitch
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