Study of near-surface stresses in silicon around through silicon vias at elevated temperatures by Raman spectroscopy and simulations
Three-dimensional (3-D) integration has emerged as an effective solution to overcome the wiring limit imposed on device density and performance with continued scaling. Through silicon vias (TSVs), which provides interconnection between stacked chips, are essential for the 3-D integration. However, d...
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| Language: | English |
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University of British Columbia
2014
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| Online Access: | http://hdl.handle.net/2429/51590 |