Single chip variable rate viterbi decoder of constraint length K = 5
This thesis presents a fully self-testable integrated circuit (IC) variable-rate Viterbi decoder of constraint length K = 5. The chip is designed to decode convolutional codes ranging from rate 7/8 to 1/4, derived from the same rate 1/2 mother code. The architecture of the Viterbi decoder is bit-...
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| Format: | Others |
| Language: | English |
| Published: |
2009
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| Online Access: | http://hdl.handle.net/2429/4924 |
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