| Summary: | This thesis presents a fully self-testable integrated circuit (IC) variable-rate Viterbi
decoder of constraint length K = 5. The chip is designed to decode convolutional codes
ranging from rate 7/8 to 1/4, derived from the same rate 1/2 mother code. The architecture
of the Viterbi decoder is bit-serial node-parallel. The incoming 8-level quantized channel
bits are input in parallel and converted to a serial stream. This reduces the amount of
interprocessor wiring area substantially, as there are only single wire connections between
the add-compare-select (ACS) units. High decoding speed is still achieved because the ACS
operation is carried out concurrentiy in each of the 16 states.
For the path memory, the register exchange technique was adopted. To reduce the ICs
silicon area, the path memory is full-custom layout. For the trellis interconnections between
consecutive memory stages, a novel state relabelling technique is proposed that reduces the
interconnect area substantially. The area savings are accomplished by redrawing the trellis
as sets of butterflies,
A major aspect of this IC is its very cost effective built-in self-test. The stuck-at fault
coverage is 99% with an overhead area of only 5%, which should not lower the manufacturing
yield significantly, and thus yield significant benefits.
A novel test algorithm was developed for the path memory. A specific but easy to
generate test pattern is applied to the inputs. A major advantage of this deterministic test
over pseudo-random techniques is that the test length is very short and, more importantly,
independent of the number of states of the Viterbi decoder. The rest of the circuit is tested by pseudo-random patterns combined with a multiple
signature analysis scheme. After finding an appropriate initial state of the test pattern
generator, it is possible to check for four identical signatures. Compared to checking only one
signature at the end of the test session, checking four identical signatures has the advantage
of reducing the probability of error escape, while avoiding complicated signature checking
for four different references. Moreover, test time can be reduced as faulty chips can be
discarded as soon as a signature does not match the reference. These advantageous features
are accomplished with circuit overhead equal to checking only a single signature at the end
of the test session. The only cost is a one-time logic simulation performed at design phase. === Applied Science, Faculty of === Electrical and Computer Engineering, Department of === Graduate
|
|---|
