Formal verification of asynchronous data-path circuits
Asynchronous designs are typically modelled with non-deterministic next-state relations. When a deterministic model is available, specialised verification techniques can be used to automatically verify relatively large designs. This thesis demonstrates that verification techniques developed for d...
| Main Author: | |
|---|---|
| Format: | Others |
| Language: | English |
| Published: |
2009
|
| Online Access: | http://hdl.handle.net/2429/4469 |