| Summary: | A wideband phase-locked loop (PLL) allows chip designers to use a single PLL for multiple communication standards. In wireline transceivers, such a wideband PLL can be incorporated as a part of a programmable (software-defined) de-serializer, or replace several PLLs for multiple standards if the bands are not used simultaneously. This thesis presents the design of a wideband PLL targeting wireline communication standards with clock frequencies between 0.5 and 5 GHz. To the author’s knowledge it is the first wideband PLL using an active-inductor-based VCO and its measured performance results compare favorably, especially in power and area, with state-of-the-art wideband PLLs. Further contributions include: the derivation of the lumped-element model of the PMOS-based two-stage active-inductor, noise contributions of the active-inductor VCO, and a compensated charge pump to reduce locked phase offsets.
Design targets a 0.13-μm CMOS process. In simulations with extracted parasitics, the active-inductor VCO covers the desired 0.5 to 5 GHz range with a small margin. It exhibits coarse and fine VCO gains of 12.8 and 1.48 GHz/V, respectively, across the entire tuning range. The phase noise of the VCO is less than or equal to –78 dBc/Hz at a 1 MHz offset from the carrier. As compared to simulations, the measured maximum operating frequency of the VCO is reduced by 12 %, spanning frequencies up to 4.4 GHz. The measured phase noise degrades by approximately 10 dBc/Hz.
The PLL uses a phase-frequency detector to lock to incoming signal across its entire frequency range and a linear compensated phase detector to achieve less than 5° phase offset between the incoming and locked clocks and a measured output jitter of 1.3 ps_rms for a VCO output frequency of 4 GHz. The PLL consumes between 34 mW and 48 mW. === Applied Science, Faculty of === Electrical and Computer Engineering, Department of === Graduate
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