Implementation and analysis of surfing pipelines

• Main Author: Yang, Suwen
• Language: English
• Published: 2009
• Online Access: http://hdl.handle.net/2429/16912

High performance digital systems make extensive use of pipelines. Three years ago, "surfing" pipelines were proposed. A timing pulse propagates through the surfing pipeline, and the individual logic elements of the pipeline are modified so that their delays are smaller in the presence of the pulse than in its absence. This creates an "event attractor" where events in the data path occur at the rising edge of the timing pulse. These attractors reduce timing uncertainties and improve the performance of the pipeline. A circuit technique called "preswitching" was proposed to implement the delay variation required for surfing. In this thesis, we demonstrate a working, surfing chip and address issues of power consumption and robustness. We demonstrate surfing by the design, fabrication and test of a chip using preswitching surfing circuits. The surfing ring in this chip supports two, independent waves of computation separated only by the surfing effect - no latches or other storage elements are used. We operated the ring for over 48 hours and 2 * 101 5 surfing events and never observed an error. The preswitching circuits in this chip exhibit unacceptable power consumption, motivating our work on energy-efficient designs. We introduce a new family of surfing circuits based on charge-sharing, dynamic gates. The design and simulation of a carry-lookahead adder show that this technique offers very competitive performance by standard metrics. This design also demonstrates surfing in a design with a non-uniform circuit structure. Finally, we develop a new method for robustness analysis. We formulate noise-margin analysis as a numerical optimization problem that takes the timevarying behavior of surfing and other dynamic logic designs into account. With this approach we compare the robustness of several, high-performance logic families, quantify the timing stability of surfing circuits, and demonstrate trade-offs between performance and robustness. Our demonstration of a physical surfing chip; design of novel; low-power surfing circuits; and a new noise-margin analysis method together bring surfing closer to a practical reality. These tools and .techniques will aid the development of novel logic designs to face the challenges of deep-submicron integrated circuit design. === Science, Faculty of === Computer Science, Department of === Graduate