Design and implementation of a high-speed data logging facility for a dual DSP system

• Main Author: Yedid Barba, Erika
• Format: Others
• Language: English
• Published: 2009
• Online Access: http://hdl.handle.net/2429/12279

This thesis has two main components: implementation and system evaluation. In the implementation phase, we port an existing real-time operating system, called ORTS, from a single processor version to a multiprocessor version, and integrate a DMA mechanism for data transfers, which has never been exploited in the previous ORTS versions. Two major disadvantages of the previous ORTS versions are: its incapability to sample at frequencies higher than 1 kHz, and the large amounts of data losses the system incurs when data is transferred between the DSP board and the host. With the aim of achieving higher sampling frequencies and improving DSP-host communication performance, ORTS was ported to a dual DSP processor board called Daytona, based on Texas Instruments TMS320C67 DSP processors running at 167 MHz. The DSP processor itself supports DMA transfers within its local memory map. In this thesis, the C67 DMA has been integrated with the real-time kernel mainly to reduce the duration of system calls to write or read data buffers (in ORTS called links) for burst transfers. A DMA algorithm and a mechanism called "tracking flags", were developed to control DMA access among all processes and allow multitasking, without locking the DMA controller to any semaphore. In the evaluation phase, we first demonstrate the existence of two previously unknown problems of ORTS that were preventing periodic processes to run periodically at the defined frequency, and provide the necessary information to fix the problems. Second, we present the static analysis for bounding the WCET of data transfers for the previous ORTS version, where no DSP instruction parallelism and DMA transfers were in play. We extend the previous analysis by presenting a method for dealing with the microarchitecture of the Tl TMS320C67 processor, which integrates VLIW technology that leads to complex instruction parallelism, and a method for bounding DMA transfers. === Applied Science, Faculty of === Electrical and Computer Engineering, Department of === Graduate