| Summary: | This thesis introduces a new specification style for processor microarchitectures. My
goal is to produce very simple, compact, but cycle-accurate descriptions that can be
automatically simulated efficiently, in order to enable early exploration of different
microarchitectures and their performance. The key idea behind my approach is that
one can derive the difficult-to-design forwarding and stall logic completely automatically.
I have implemented a specification language for pipelined processors, along
with an automatic translator that creates cycle-accurate software simulators from
the specifications. I have specified a pipelined MIPS integer core in my language.
The entire specification is less than 300 lines long and implements all user-mode instructions
except for coprocessor support. The resulting, automatically-generated,
cycle-accurate simulator achieves over 240,000 instructions per second simulating
MIPS machine code. This performance is within an order of magnitude of large,
hand-crafted, cycle-accurate simulators, but my specification is far easier to create,
read, and modify. === Science, Faculty of === Computer Science, Department of === Graduate
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