Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures

Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures

Show other versions (1)

MAPPING AND OPTIMIZING A SOFTWARE-ONLY REAL-TIME Due to its high computational demand, MPEG-2 video coding solutions have been based mainly on custom hardware (ASIC) systems. Such systems lack the flexibility and adaptability of software-based solutions. Achieving real-time MPEG-2 video encoding i...

Full description

Bibliographic Details
Main Author:	Lee, Henry
Format:	Others
Language:	English
Published:	2009
Online Access:	http://hdl.handle.net/2429/10276

Similar Items

Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures
by: Lee, Henry
Published: (2009)

Variable-Length VLIW Encoding & its Decoding Architectures
by: Chia-Hsien Liu, et al.
Published: (2005)

Optimizing VLIW architectures for multimedia applications
by: Salamí San Juan, Esther
Published: (2007)

Optimizing the GCC Suite for a VLIW Architecture
by: Strätling, Adrian
Published: (2004)

Optimizing the GCC Suite for a VLIW Architecture: Optimierung der GCC Suite für eine VLIW Architektur
by: Strätling, Adrian
Published: (2004)

Optimizing an H.264 video encoder for real-time HD-video encoding
by: Hermansson, Per
Published: (2011)

On-line Real-time Fault-Tolerant VLIW Processor
by: HSUEH CHUNG LIU, et al.
Published: (2002)

On loop scheduling for homogeneous VLIW architecture
by: YU, JUN-YI, et al.
Published: (1992)

Design and evaluation of a VLIW processor for real-time systems
by: Starke, Renan Augusto
Published: (2016)

Porting the GCC-Backend to a VLIW-Architecture
by: Parthey, Jan
Published: (2004)

Improving multithreading performance for clustered VLIW architectures.
by: Gupta, Manoj
Published: (2013)

Optimisation of video coding algorithms for VLIW-type processors
by: Sohm, Oliver Peter
Published: (2003)

Porting the GCC-Backend to a VLIW-Architecture: Portierung des GCC-Backends auf eine VLIW-Architektur
by: Parthey, Jan
Published: (2004)

Enabling Software Pipelining for PAC VLIW DSP Processors
by: Shih-Chang Chen, et al.
Published: (2006)

Selective Code Duplication for Soft Error Protection on VLIW Architectures
by: Yohan Ko, et al.
Published: (2021-07-01)

Compilers for VLIW DSP Architectures with Distributed and Irregular Designs
by: Yung-Chia Lin, et al.
Published: (2007)

A flexible compilation infrastructure for VLIW and SIMD architectures
by: Maze, David Z. (David Zachary), 1978-
Published: (2014)

Code compaction and parallelization for VLIW/DSP chip architectures
by: Petrov, Tsvetomir P. (Tsvetomir Petrov), 1974-
Published: (2013)

Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures
by: Haijing Tang, et al.
Published: (2013-01-01)

Variable-Length VLIW Encoding for TI C64x DSP Processors
by: Bo-Yu Su, et al.
Published: (2014)

A clustered VLIW architecture based on queue register files
by: Fernandes, Marcio Merino
Published: (1998)

Improving ILP with the Vectorized Computing Mechanism in VLIW DSP Architecture
by: Te-Shin Yang, et al.
Published: (2003)

A Parallel Processing Framework for Real-Time Software-Only Video Compression for Broadcast and Mobile Services
by: Zheng, L., et al.
Published: (2006-12-01)

Aggressive Inlining for VLIW
by: A. . Ermolitckii, et al.
Published: (2018-10-01)

Performance enhancing software loop transformations for embedded VLIW/EPIC processors
by: Akturan, Cagdas, 1973-
Published: (2011)

Performance optimization mechanisms for fault-resilient VLIW processors
by: Psiakis, Rafail
Published: (2018)

Compiler-Assisted Energy Optimization For Clustered VLIW Processors
by: Nagpal, Rahul
Published: (2010)

Global microcode compaction using priority setting and duplication for VLIW architectures
by: WENG,LI-QI, et al.
Published: (1991)

A study on hierarchical register file for loop scheduling in VLIW architecture
by: YANG,WEN-XIN, et al.
Published: (1991)

A Power-aware Code-compression Scheme for RISC/VLIW Architecture
by: Che-wei Lin, et al.
Published: (2010)

Improving instruction set design of embedded microcontroller architecture based on Transport-Triggered Architecture and VLIW
by: Albert Wang, et al.
Published: (2005)

Loop Optimization and Performance Evaluation for a Homogeneous VLIW Computer
by: Huang, Chung Ren, et al.
Published: (1994)

Adapting a Constraint-Based Compiler Tool to a New VLIW Architecture
by: Kjellin, Martin
Published: (2019)

Improving the Fetching Performance of Instruction Stream Buffer for VLIW Architectures with Compressed Instructions
by: Kai-Ming Yang, et al.
Published: (2006)

Convergent scheduling : a flexible and extensible scheduling framework for clustered VLIW architectures
by: Puppin, Diego, 1976-
Published: (2014)

Concurrent Real Time Video Encoding for PC-Based Digital Video Recorder
by: 張思默
Published: (2003)

Chip Design Tradeoffs for a VLIW Processor
by: Ton, Lee Rern, et al.
Published: (1995)

Compiler Optimizations for a UnifiedVLIW-based RISC/DSP Processor
by: Tsung-Hua Hsueh, et al.
Published: (2007)

Global Optimizations in Compilers for VLIW DSP Processors with Distributed Register Files
by: Wu, Chung-Ju, et al.
Published: (2015)

Explicit Simultaneous Multithreaded Architectures for VLIW DSPs via Dynamic Split-Issue Mechanism
by: Jih-Sheng Wu, et al.
Published: (2005)