Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures
MAPPING AND OPTIMIZING A SOFTWARE-ONLY REAL-TIME Due to its high computational demand, MPEG-2 video coding solutions have been based mainly on custom hardware (ASIC) systems. Such systems lack the flexibility and adaptability of software-based solutions. Achieving real-time MPEG-2 video encoding i...
Main Author: | |
---|---|
Format: | Others |
Language: | English |
Published: |
2009
|
Online Access: | http://hdl.handle.net/2429/10276 |
id |
ndltd-UBC-oai-circle.library.ubc.ca-2429-10276 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-UBC-oai-circle.library.ubc.ca-2429-102762018-01-05T17:35:13Z Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures Lee, Henry MAPPING AND OPTIMIZING A SOFTWARE-ONLY REAL-TIME Due to its high computational demand, MPEG-2 video coding solutions have been based mainly on custom hardware (ASIC) systems. Such systems lack the flexibility and adaptability of software-based solutions. Achieving real-time MPEG-2 video encoding in software remains to be a major challenge. A typical MPEG-2 encoder performs 20 to 30 GOPS (giga operations per second), which exceeds the capabilities of the most advanced contemporary processors. In this thesis, we have developed and tested a highly optimized, low complexity, highquality MPEG-2 video encoder software based on Texas Instruments' fixed-point TMS320C6201 VLiW (Very Long Instruction Word) processor. First, we developed MPEG-2 video encoder software written in C for the C62x processor platform, however, due to the difference in the processor architecture, optimization and modification are done on the software to ensure the MPEG-2 video encoder runs efficiently in the VLIW architecture. The optimization are done at the assembly language level to maximize the attainable instruction-level parallelism (ILP) of the C62x VLIW architecture. In our experience, optimizations done alone by the optimizing Ccompiler of the C62x could not meet the real-time requirements of MPEG-2. After code remapping and optimization, the resulting MPEG-2 video encoder implementation runs approximately 32 times faster than the original unoptimized MPEG-2 video encoder. Moreover, the current version of the encoder can handle SIF(320x240) video format at 16 frames per second with both I and P pictures, and CCIR-601 (720x480) at 15 frames per second for the I pictures only. Our real-time MPEG-2 encoder has been implemented and tested on the C62x Evaluation Model (EVM) board from TI. Applied Science, Faculty of Electrical and Computer Engineering, Department of Graduate 2009-07-06T21:53:54Z 2009-07-06T21:53:54Z 2000 2000-05 Text Thesis/Dissertation http://hdl.handle.net/2429/10276 eng For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. 4562148 bytes application/pdf |
collection |
NDLTD |
language |
English |
format |
Others
|
sources |
NDLTD |
description |
MAPPING AND OPTIMIZING A SOFTWARE-ONLY REAL-TIME Due to its high computational demand, MPEG-2 video coding solutions have been based
mainly on custom hardware (ASIC) systems. Such systems lack the flexibility and adaptability of
software-based solutions. Achieving real-time MPEG-2 video encoding in software remains to
be a major challenge. A typical MPEG-2 encoder performs 20 to 30 GOPS (giga operations per
second), which exceeds the capabilities of the most advanced contemporary processors.
In this thesis, we have developed and tested a highly optimized, low complexity, highquality
MPEG-2 video encoder software based on Texas Instruments' fixed-point TMS320C6201
VLiW (Very Long Instruction Word) processor. First, we developed MPEG-2 video encoder
software written in C for the C62x processor platform, however, due to the difference in the
processor architecture, optimization and modification are done on the software to ensure the
MPEG-2 video encoder runs efficiently in the VLIW architecture. The optimization are done at
the assembly language level to maximize the attainable instruction-level parallelism (ILP) of the
C62x VLIW architecture. In our experience, optimizations done alone by the optimizing Ccompiler
of the C62x could not meet the real-time requirements of MPEG-2. After code remapping
and optimization, the resulting MPEG-2 video encoder implementation runs
approximately 32 times faster than the original unoptimized MPEG-2 video encoder. Moreover,
the current version of the encoder can handle SIF(320x240) video format at 16 frames per second
with both I and P pictures, and CCIR-601 (720x480) at 15 frames per second for the I pictures
only. Our real-time MPEG-2 encoder has been implemented and tested on the C62x Evaluation
Model (EVM) board from TI. === Applied Science, Faculty of === Electrical and Computer Engineering, Department of === Graduate |
author |
Lee, Henry |
spellingShingle |
Lee, Henry Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures |
author_facet |
Lee, Henry |
author_sort |
Lee, Henry |
title |
Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures |
title_short |
Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures |
title_full |
Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures |
title_fullStr |
Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures |
title_full_unstemmed |
Mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures |
title_sort |
mapping and optimizing a software-only real-time mpge-2 video encoder on vliw architectures |
publishDate |
2009 |
url |
http://hdl.handle.net/2429/10276 |
work_keys_str_mv |
AT leehenry mappingandoptimizingasoftwareonlyrealtimempge2videoencoderonvliwarchitectures |
_version_ |
1718588504960663552 |