| Summary: | 碩士 === 國立交通大學 === 國際半導體產業學院 === 108 === Monolithic 3D-IC is an enabling technology for reducing chip size and power consumption and enhancing the overall system performance and using BEOL circuits. To avoid damaging transistors on the bottom silicon layer, low thermal budget is required for while fabricating polycrystalline BEOL circuits on top layers. However, if polycrystalline semiconductor is used, the yield of Monolithic 3D technology is decreased by the random grain boundaries of Si grains. In this thesis, SRAM design using the Location-Controlled-Grain (LCG) technique is presented to reduce the overall bit error rate (BER). Moreover, a graph-based statistical BER analysis is adopted using both transistor-level and cell-level boundary assignments for random grains. The BER of LCG SRAM can be significantly reduced.
The defects of monolithic 3D BEOL circuits is still one of design challenges in monolithic 3D SRAM. Instead of placing SRAM cells on BEOL layers, WL-boosted repeaters and ripple-BL buffers are proposed using monolithic 3D BEOL FinFETs to decrease the catastrophic RC effect of SRAM in sub-10nm technologies. The WL-boosted repeaters and ripple-BL buffers can achieve 24.8% delay reduction and 19.6% area reduction, respectively.
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