Aggregating and Disaggregating A Non-fixed Number of Packets with Various Sizes in P4 Switches at Line Rate

• Main Authors: Li, Jun-Yi, 李俊毅
• Other Authors: Wang, Shie-Yuan
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/r5a3yj

碩士 === 國立交通大學 === 網路工程研究所 === 108 === Aggregating multiple small-sized packets into a large packet provides many advantages. For example, multiple small packets can share a single copy of common Ethernet/IP/UDP headers to reduce the percentage of network bandwidth wasted on transmitting headers. In the past, packet aggregation and disaggregation were done by server CPU or switch CPU, resulting in low throughputs. In the thesis, we design and implement the packet aggregation and disaggregation functions in the packet processing pipelines of P4 switches. Our novel designs allow a non-fixed number of packets with various sizes to be aggregated and disaggregated purely in the data plane of the P4 switch. As a result, the achieved throughputs of our aggregation and disaggregation methods can reach the 100 Gbps line rate of the used P4 switches.