Design and Analysis of Front-End Circuits for W-band Transceiver System

• Main Authors: Huang, Ching-Ying, 黃瀞瑩
• Other Authors: Chiang, Chi-Yang
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/437fw9

博士 === 國立交通大學 === 電信工程研究所 === 108 === With maximum operating frequency in hundreds of gigahertz, today’s silicon processing technologies show great promise for commercial millimetre-wave applications. If silicon process be used in radio-astronomical telescopes, it could facilitate the development of large multi-pixel focal plane arrays up to W-band and beyond. To develop a receiver system, which covers overall W-band frequency, we start with the design of W-band receiver where RF-LNA, wideband mixer, IF amplification, LO tripler and driving amplifier are all integrated into one single chip of 1050×820μm2. To effectively extend the mixer’s IF bandwidth while retaining its conversion gain, impacts of the mixing transistor’s drain bias and output loading impedance are explored using dual-modulation conversion-matrix method, which allows both the LO-induced transconductance modulation and channel-conductance modulation to be considered simultaneously. It is shown that, by merging the input capacitance of the IF amplifier into a high-impedance artificial transmission line, an actively-biased mixer can have constant conversion gain over broad bandwidth. A 77–110GHz 65nm-CMOS receiver with 33GHz IF bandwidth is then designed and measured. Its conversion gain and noise figure are 10dB and 20dB, respectively, and the input-referred P1dB is -15dBm; the overall power consumption is 330mW under 1.3V drain bias. Besides, we investigate the insertion loss of the broadband 8-way power combiner used in our millimeter-wave power amplifier design. By treating this combiner as impedance-transformer under RC loading condition, both the characteristic impedance and electrical length of the constituting metal lines can be obtained where the much shorter line length suggests wider bandwidth and lower insertion loss (IL). However, proper loss analysis must take into account the multi-reflection of voltage wave along these mismatched transmission lines, i.e., the use of the power attenuation expression e^(-2αL) is just not accurate enough. With our derived equations, it shows that the insertion loss of our proposed 8-way combiner can be as low as 0.92dB at 94GHz, which is much smaller than the 1.5dB for the conventional quarter-wavelength combiner. Mathematics for the insertion loss of the drain-bias shunt stub and the output DC-blocking capacitor have also been derived. As a demonstration, a 77~110 GHz 40nm-CMOS PA made of cascode transistors is then designed that has more than 18dB gain and its OP1dB is around 13dBm across the whole frequency range. According to the need of the system, a new wideband active power splitter design where the gain cells along the input transmission line are arranged in interleaf rather than the conventional parallel style, thus the circuit’s high-frequency performance can be greatly improved. Both theoretical analysis and circuit simulation have been carried out; as a demonstration, parallel and interleaf active power splitters are designed using 0.1μm-GaAs pHEMT process and measured on-wafer. The results clearly indicates the superiority of the interleaf topology. A 40GHz interleaf active power splitter in 90nm-CMOS is then presented where the magnitude and phase imbalance between the two output ports are 0.15dB and 2.6o at 20GHz, and 0.16dB and 14o at 40GHz. The output-port isolation is better than 30dB across the whole frequency range.