Timing Driven Partition on Multi-FPGA System with Predictive TDM Estimation
碩士 === 國立交通大學 === 電子研究所 === 108 === Multi-FPGA system is a popular approach to achieve hardware acceleration with the scalability to accommodate large designs. The problem on design partition to improve emulator performance is a non-trivial problem due to the connectivity constraint between FPGAs an...
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| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/ktd6c5 |
| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 108 === Multi-FPGA system is a popular approach to achieve hardware acceleration with the scalability to accommodate large designs. The problem on design partition to improve emulator performance is a non-trivial problem due to the connectivity constraint between FPGAs and the resource constraint that limits the amount of logic placed on each FPGA.
To overcome the connectivity constraint, time-division multiplexing (TDM) is adopted to deliver multiple signals over a single wire at the expense of additional delay for shared signals.
In this work, a timing driven partition methodology considering hardware configuration of the emulator and timing critical paths is proposed. Critical paths are identified and optimized with the guidance of analytical placer.
Delay introduced by TDM is estimated and optimized using look-up table for better efficiency.
Compared with conventional metric using cut, our work can achieve 43\% improvement.
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