A Low Latency NN-based Cyclic Jacobi EVD Processor for DOA Estimation in Radar System

碩士 === 國立交通大學 === 電子研究所 === 108 === The development of radar technology has always been a hot issue. Especially in recent years, because of the popularization of Advanced Driver Assistance Systems (ADAS), such as autonomous driving system and collision avoidance system, the requirements for radar te...

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Bibliographic Details
Main Authors: Huang, Kang-Chun, 黃綱俊
Other Authors: Liu, Chih-Wei
Format: Others
Language:en_US
Published: 2019
Online Access:http://ndltd.ncl.edu.tw/handle/822kq2
Description
Summary:碩士 === 國立交通大學 === 電子研究所 === 108 === The development of radar technology has always been a hot issue. Especially in recent years, because of the popularization of Advanced Driver Assistance Systems (ADAS), such as autonomous driving system and collision avoidance system, the requirements for radar technology are rapidly increasing. By the radar system and the digital signal processing, we can get the object’s information, such as range, velocity and angle information. This thesis will focus on the angle detection part. We use the MUSIC (MUltiple SIgnal Classification) algorithm for high resolution requirement, which is a kind of super resolution algorithm. In MUSIC algorithm, EVD (Eigenvalue Decomposition) costs the most computation load. We use Cyclic Jacobi method to implement EVD processor, which can achieve hardware simplification and eliminate off-diagonal elements to zero. We propose to use the neural network model training arctangent, sine and cosine function and implement those models in hardware, which are used for plane rotation in cyclic Jacobi algorithm. We use the Static Floating-Point (SFP) arithmetic in our neural network model, which can operate on the most efficient bits. The SFP arithmetic has the higher accuracy than the fixed point arithmetic. The neural network model for trigonometric function has lower latency than the CORDIC method. We implement a NN-based Cyclic Jacobi EVD processor in TSMC 90 nm CMOS technology with high-Vt standard cell library. The latency of the system is 1.25 us, the total gate counts are 104.401k, and the power consumption is 15.4 mW (@0.9V).