| Summary: | 碩士 === 元智大學 === 電機工程學系甲組 === 107 === With the development of RF soft defined ratio(SDR), Programmable Gain Amplifier (PGA) was widely applied in applications of wide-bandwidth communication, bio-potential acquisition and high accuracy signal measurement to optimize the system performance among different operation conditions. This paper overview and compare the architecture of reported papers and commercial ICs of PGA. To design a PGA used in wireless communication system, this paper proposes a PGA design which features a wider linear input range. The proposed PGA is composed of a coarse-tune cascaded amplifier with 8dB of gain resolution, a fine-tune cascaded amplifier with 0.5dB of gain resolution and a path-selection multiplexer. Under external 7-bits digital control, the proposed PGA has a total of 127 gain path and has an adjustable gain range from -8dB to 56dB.
To ensure the gain under different process variation, a gain calcination feedback network was added to the proposed PGA. To analysis the gain calcination feedback network, a transistor-level small signal mode of PGA was built to obtain the digital transfer function. The error between the calculation and verification simulation was about 10%.
As a chip-level verification, TSMC 0.18um was used to realize the proposed 7-bits PGA. The post-layout simulation results show that the active area was 0.494- mm2, the operational bandwidth was 10MHz, the dynamic range of gain was 63.5dB. The INL and DNL of gain are respectively Xdb and YdB, respectively. The power consumption of overall design was 4.5mW.
Keyword: Programmable Gain Amplifier, Variable Gain Amplifier, Gain Calabrian, Process Variation, Linear Input Range, Source Degeneration Resistor.
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