| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === This thesis proposes a dual-output voltage mode buck with a tapped inductor. The general single-inductor multi-output uses a traditional inductor. The main feature of this paper is to extend the duty cycle of the tapped inductor to achieve a larger step-down ratio, and to extend the responsibility. The extend cycle reduces the peak current of the upper power stage switch to improve the switching loss, operates the inductor current in continuous conduction mode, and uses phase sequence scheme to suppress the cross regulation phenomenon.
This thesis is implemented in the TMSC 0.35 m 2P4M 3.3/5 V mixed-signal CMOS process. The wafer area of the wafer containing PADs is 1.7×3.342 mm2. The input voltage is 5 V, the output voltage is 1.8 V and 1.2 V respectively, the output load range is 50-400 mA, the external power stage tapped inductance is 4.7 H, the turns ratio is 1.5, and the output capacitance is 10 F. The simulation results have a cross-regulated voltage of 0.125-0.175 mV/mA. The maximum efficiency of the converter is 92.3% for each of the two outputs of 100 mA, and the lowest efficiency is 89% for each of the two outputs of 400 mA.
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