The Design and Verification of an IP Core for Pipeline AES Based on AXI4 Interface

• Main Authors: Yu-Sung Chang, 張祐菘
• Other Authors: Ming-Bo Lin
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/t2z5np

碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === In this thesis, a pipelined architecture of AES Encryption/Decryption based on AXI4 interface is proposed. This architecture emphasizes area and throughput, reduces hardware cost and improves its computing performance. According to the AES algorithm, the input data is 128 bits and the cipher key has three options: 128, 192 or 256 bits. In order to reduce area and improve its computing performance, we use an inner-round pipelining architecture, combining Encryption and Decryption to share hardware. The composite field arithmetic is used in Subbytes transformation. Simplify the algorithm by finding the same operators for Mixcolumn/Invmixcolumn transformation. An on-the-fly key architecture is used in KeyExpansion to reduce area of memory. In complex SoC design, it often needs a bus, which has high performance and low latency. Therefore, we select AMBA4.0 AXI interface, which is widely used in industry. The pipeline architecture of AES Encryption/Decryption IP has been implemented and verified with both Xilinx Virtex 5 (XC5VLX110T) and TSMC 0.18 µm cell library. In the FPGA part, it uses 2562 registers and 4829 LUTs, operates at 200 MHz and can achieve a high throughput of 2327 Mbps. In the cell-based part, it operates at 142.85 MHz and can achieve a high throughput of 1662 Mbps. The core occupies an area of 874.145 µm × 872.265 µm, which is approximately equivalent 48537 gates, and consumes about 33.43 mW in the typical operating condition.