The Design and Implementation of an AXI4-Compatible DDR4-SDRAM Controller

• Main Authors: YEN-LIN LUNG, 龍彥霖
• Other Authors: Ming-Bo Lin
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/jttm8m

碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === In the era of more and more complex functions in SoC (System on Chip), the access to data is so huge that how to improve the access speed of the memory is an important issue. Although the clock of memory continues to increase, its access speed is still much lower than the processor speed. Therefore, to increase the performance of the SoC, it is necessary to improve the performance of memory access. For this reason, it is important to design an efficient memory controller. The ARM Cortex series of microcontrollers are widely used in SoC chips, so this thesis designed an SDRAM controller that conforms to the AXI4 interface in the AMBA series and conforms to the SDRAM DDR4 interface. The SDRAM controller is divided into four blocks, which are asynchronous receiving AXI4 instruction block, instruction scheduling block, memory physical layer block, and memory data return block. By exploiting the properties of the burst type transmission and AXI random transmission, combined with the characteristics of the DDR4 bank groups and proper priority scheduling, can effectively reduce the waiting time required for access, thereby improving the memory access performance. The completed memory controller conforms to the DDR4 SDRAM and AMBA series AXI4 specifications and can make the most efficient access process according to different access conditions. Synthesis and simulation are performed on the Xilinx ISE Virtex6. A total of 643 logic gates and 813 registers are used, and 465 LUTs are used as the memory. The highest frequency after frequency multiplication was 245.28 MHz.