The Design and Implementation of the Frequency-Drift-Compensated Phase-Locked Loop

• Main Authors: Cheng-En Hsieh, 謝正恩
• Other Authors: 劉深淵
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/jj9jr8

博士 === 國立臺灣大學 === 電子工程學研究所 === 107 === This dissertation consists of two parts. The first part aims to design a frequency-drift-compensated (FDC) phase-locked loop (PLL). The second part implements a 10 bit analog-to-digital converter (ADC) which uses to increase the resolution of the frequency-drift compensator. First, the lossy LC-tank of a voltage-controlled oscillator (VCO) will induce the frequency drift due to the temperature variations. If the drifting frequency is larger than the tuning range of an LC-VCO, the PLL will unlock and cannot be a stable clock generator. To sense the drifting frequency of the LC-VCO, a 6 bit successive-approximation-register (SAR) ADC is used due to its small area and low power characteristics. The FDC adjusts the capacitor banks of the LC-VCO to compensate the frequency drift owing the temperature variations. The average temperature coefficient (TC) is 2.43 ppm/°C from 20 °C to 100 °C. The measured phase noise of this PLL is -108.32 dBc/Hz and -130.26 dBc/Hz at the frequency offset of 1 and 10 MHz, respectively. The measured reference spur at 75 MHz offset is -65.15 dBc. The total power dissipation of this PLL is 6.32 mW. The compensator area of the previous arts always occupied 10~15% of the active area however this FDC used only 1.26% of the active area for the temperature compensation. Second, increasing the resolution of the FDC and the number of the capacitor banks can improve the TC and the temperature compensation range of the PLL, respectively. Therefore, the ADC resolution is design to 10 bit. The power consumption can be decreased by reducing the supply voltage. However, the intrinsic gain, operation region, and headroom of transistors deteriorates analogy circuits due to a low supply voltage. To overcome the above issues, a double-boosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. This ADC achieves the measured SNDR of 54.57 dB, which exhibits an effective number of bit (ENOB) of 8.77 bit without missing code. The total power dissipation is 15.9 nW. A figure-of-merit (FOM) of 7.3fJ/conversion-step for this ADC is achieved.