A 1.5-6 Gb/s Clock and Data Recovery Circuit Reducing Cycle Slipping
碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === The proposed CDR circuit is simulated in 40-nm CMOS technology. While the supply is 1-V, the CDR circuit can operate with the data rate of 1.5-6 Gb/s. The power consumption is about 4.43mW when the input data rate is 6Gb/s. According to the simulation results,...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73sfsy |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === The proposed CDR circuit is simulated in 40-nm CMOS technology. While the supply is 1-V, the CDR circuit can operate with the data rate of 1.5-6 Gb/s. The power consumption is about 4.43mW when the input data rate is 6Gb/s. According to the simulation results, it can prove that the proposed CDR circuit is able to track the frequency bi-directionally, and acquire the data rate again if the data rate changes or a noise on control voltage make the clock frequency change. Also, it is reduced with the cycle slipping issue which happens a lot in traditional dual-loop CDRs. And the frequency acquisition time is improved, too.
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