A PVT-Tolerant MDLL with a Background Coarse-Frequency Selector and a Frequency Calibrator using a Delay-Calibrated SSPD
碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === A multiplying delay-locked loop (MDLL) with a background coarse-frequency selector and a frequency calibrator is presented. To reduce the reference spur due to the frequency error, a frequency calibrator using a delay-calibrated SSPD is presented. The phase noi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82qmnk |