A PVT-Tolerant MDLL with a Background Coarse-Frequency Selector and a Frequency Calibrator using a Delay-Calibrated SSPD
碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === A multiplying delay-locked loop (MDLL) with a background coarse-frequency selector and a frequency calibrator is presented. To reduce the reference spur due to the frequency error, a frequency calibrator using a delay-calibrated SSPD is presented. The phase noi...
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| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82qmnk |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === A multiplying delay-locked loop (MDLL) with a background coarse-frequency selector and a frequency calibrator is presented. To reduce the reference spur due to the frequency error, a frequency calibrator using a delay-calibrated SSPD is presented. The phase noise of the CP and the SSPD is not multiplied by N2. To cover a wide frequency variation, the background coarse-frequency selector is also presented. This MDLL is fabricated in 40-nm CMOS technology. The active area is 0.013mm2, and the power consumption is 5.2mW from a supply of 1V. It exhibits a root-mean-square jitter of 229fs at 2.4GHz output and the reference spur of -54.3dBc under a reference clock of 150MHz.
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