| Summary: | 碩士 === 國立臺灣師範大學 === 機電工程學系 === 107 === In the history of the development of OTP memory, many existing structures of fuse breakdown devices used a narrow wire of metal or poly-silicide wire. On the other hand, anti-fuse breakdown devices formed an electrically conductive path permanently in the dielectric after a large external electric field applying on the gate. Based on a dielectric fuse breakdown that was discovered in our research group, further applications have been employed in the application of nonvolatile memory on a FinFET platform. In this work, we use the experiments to understand the difference in the characteristics of the fuse and anti-fuse breakdown mechanisms and by taking this advantage to develop a 2-bit-per-cell OTP memory with Physically Unclonable Function.
First, our memory cell consists of two breakdown mechanism in one cell including anti-fuse breakdown and dielectric fuse breakdown, which are used to achieve the purpose of data storage. Furthermore, we use the TCAD simulation to investigate the electric field distribution of the device when it operates in a high voltage, and discuss the reason of two breakdown phenomenon occurs in one device. We also try to vary the supply voltage and temperature to investigate the corresponding programming time in two breakdown mechanisms.
Finally, based on this new scheme, we designed a novel 2-bit-per-cell OTP PUF, which has a larger on/off current ratio compared to that of reported results. Using the 2-bit-per-cell device can dramatically decrease the layout area and achieve high density. The experimental results show that this architecture still has excellent data retention, disturb immunity, and high security. Finally, a 2-bit-per-cell OTP PUF has been demonstrated successfully on a 14nm FinFET platform to meet the requirements of security applications in IoT era.
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