Algorithm and Architecture Designs for Efficient Layered LDPC Decoders

博士 === 國立清華大學 === 電機工程學系所 === 107

Bibliographic Details
Main Authors:	Li, Mao-Ruei, 李茂睿
Other Authors:	Ueng, Yeong-Luh
Format:	Others
Language:	en_US
Published:	2018
Online Access:	http://ndltd.ncl.edu.tw/handle/e8z22e

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spelling	ndltd-TW-107NTHU54410012019-05-16T00:52:41Z http://ndltd.ncl.edu.tw/handle/e8z22e Algorithm and Architecture Designs for Efficient Layered LDPC Decoders 高硬體效能的階層式低密度奇偶檢查解碼器架構與演算法設計 Li, Mao-Ruei 李茂睿博士國立清華大學電機工程學系所 107 Ueng, Yeong-Luh 翁詠祿 2018 學位論文 ; thesis 133 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	博士 === 國立清華大學 === 電機工程學系所 === 107
author2	Ueng, Yeong-Luh
author_facet	Ueng, Yeong-Luh Li, Mao-Ruei 李茂睿
author	Li, Mao-Ruei 李茂睿
spellingShingle	Li, Mao-Ruei 李茂睿 Algorithm and Architecture Designs for Efficient Layered LDPC Decoders
author_sort	Li, Mao-Ruei
title	Algorithm and Architecture Designs for Efficient Layered LDPC Decoders
title_short	Algorithm and Architecture Designs for Efficient Layered LDPC Decoders
title_full	Algorithm and Architecture Designs for Efficient Layered LDPC Decoders
title_fullStr	Algorithm and Architecture Designs for Efficient Layered LDPC Decoders
title_full_unstemmed	Algorithm and Architecture Designs for Efficient Layered LDPC Decoders
title_sort	algorithm and architecture designs for efficient layered ldpc decoders
publishDate	2018
url	http://ndltd.ncl.edu.tw/handle/e8z22e
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Algorithm and Architecture Designs for Efficient Layered LDPC Decoders

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