A Study on Channel Thickness Effect of Double-Gate Polycrystalline-Silicon Junctionless Thin-Film Transistors

• Main Authors: Li-Wei Yu, 游禮維
• Other Authors: Cheng-Yu Ma
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/4j5mnq

碩士 === 國立中山大學 === 電機工程學系研究所 === 107 === In this paper, the effect of different channel thickness on the Junctionless Thin Film Transistor is discussed, and also the upper gate and double gate are concerned. The channel thickness is divided into three channel thicknesses: 10nm, 8nm and 5nm. According to the measurement results, the thickness of the 10 nm channel is not controlled by upper gate, and it is necessary to use the double gate to improve. Therefore, the 8 nm and 5 nm channel thickness would be discussed subsequently in the later discussion. The on/off characteristics, the drain-induced barrier lowering, the short channel effect, and the leakage current characteristics are discussed in the devices of channel thickness 8 nm and 5 nm, respectively. It can be found that the channel thickness of 8nm and 5nm devices can improve the subthreshold swing by using double gate. This is because the gate control capability is improved, and the better the gate control capability can be seen when the channel is thinned to 5nm. Therefore, it is known that the device of channel thickness 5 nm and using double gate have the best immunity to short channel effect.