Electrical Analysis and Reliability in Advanced Metal Oxide Semiconductor Capacitance and Metal Oxide Semiconductor Field Effect Transistors / Fin Field Effect Transistors

• Main Authors: Hsi-Wen Liu, 劉錫紋
• Other Authors: Ting-Chang, Chang
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/r9ts9h

博士 === 國立中山大學 === 物理學系研究所 === 107 === Metal-oxide-semiconductor-field-effect transistors (MOSFETs) have the advantages of low manufacturing cost, low power consumption and easy scaling down. They are widely used in the IC industry, and the MOSFETs continue to shrink with the Moore''s Law. When the gate oxide layer is shrunk to a thickness of only 1 nm, the quantum tunneling effect becomes very serious at this scale, resulting in extremely large gate leakage and reliability problems. To continue the scaling down, gate leakage current is the primary problem that must be solved. Therefore, high dielectric constant oxides have been introduced as a solution. The high dielectric constant oxide is grown on the top of SiO2, which allows the gate oxide layer to have a thicker physical thickness and better transistor characteristics. Among many high dielectric constant materials, hafnium-based oxide is the most suitable material for high dielectric gate oxide due to its comprehensive properties. However, pure HfO2 has a low crystallization temperature. It is easy to crystallize after high temperature treatment, causing an increase in gate leakage current. Therefore, additional elements such as N, Si, Al, Ti, Ta and La have been doped into the high-k gate dielectrics to increase crystallization temperature. In addition, dipole can be formed in the oxide layer due to the difference in oxygen density. The dipole can be used to modulate the threshold voltage. The first part of this dissertation uses metal-oxide-semiconductor capacitance (MOSCAP) to investigate the doping dipole in HfO2 effect the electrical characteristic and reliability. We found that the capacitance of gate oxide is increased and gate leakage is decreased in dipole doped sample, but in positive bias temperature instability (PBTI) test is deteriorates severely in dipole doped sample. We consider the explanation is energy band bending due to dipole which causing the electrons has more kinetic energy after tunneling from Si to HfO2, so it is easier to trap and generate defects. In addition, time dependent dielectric breakdown (TDDB) reliability statistics shows the dielectric breakdown correspond to the Weibull distribution, and the dipole doped sample has a shorter lifetime under the same gate voltage. In the second part, we use our laboratory''s low temperature supercritical fluid processing technology to perform supercritical hydridation, fluoridation, and nitridation on MOSCAPs. In the supercritical hydridation and fluoridation treatment, There is no obvious change in the electrical characteristics for control sample and dipole sample., but in the reliability test of TDDB, the lifetime of both devices becomes longer. We think this is because supercritical hydridation and fluoridation can repair dangling bond at HfO2/SiO2 interface. In the third part, we used MOSFET to compare the effects of hot carrier degradation (HCD) of zirconium doped into HfO2. Previous n-MOSFET studies have shown that zirconium-doped hafnium oxide reduces charge trapping and improves PBTI. In this study, a significant reduction in HCD was observed with zirconium-doped HfO2 because channel hot electrons (CHE) trapping in pre-existed defects in HfO2 are the main degradation mechanisms. However, this reduced HCD becomes ineffective at ultra-low temperatures because CHE captured in deep defects at ultra-low temperatures, while zirconium doping only passes defects with shallower energy depths. Finally, p-type FinFETs were used and found an abnormal gate induced gate leakage (GIDL) occurred in the linear operation region after the 120-degree negative bias temperature instability (NBTI). The GIDL diminished when returning to room temperature. As a result, we believe that the linear region GIDL is mainly caused by (1. thermal emission and (2. interface defects at gate to drain overlap regions assisted tunneling. we used the 30-degree hot carrier degradation as a verification. There shows no GIDL in linear region after the 30-degree HCD, however, when the temperature was raised to 120 degrees, the linear region GIDL was measured.