Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture
碩士 === 國立彰化師範大學 === 電子工程學系 === 107 === This thesis presents a fully-MOSFET band-gap voltage reference circuit with low temperature coefficient. The circuit consists of a generator of PTAT, a generator of CTAT and a current source. The generator of PTAT utilize the self-cascade MOSFETs to generate th...
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ndltd-TW-107NCUE54280062019-11-06T03:33:28Z http://ndltd.ncl.edu.tw/handle/vhax89 Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture 自我疊接架構的全MOS帶隙參考電壓電路 Wang, Wei-Shin 王惟昕 碩士 國立彰化師範大學 電子工程學系 107 This thesis presents a fully-MOSFET band-gap voltage reference circuit with low temperature coefficient. The circuit consists of a generator of PTAT, a generator of CTAT and a current source. The generator of PTAT utilize the self-cascade MOSFETs to generate the PTAT voltage, and the generator of CTAT is a MOSFET gate to source voltage, this voltage is a CTAT voltage when the MOSFET is operated in sub-threshold region. We use TSMC 0.18 μm CMOS technology to design the circuit in this thesis. The pre-simulation results are when VDD is at 1.8 V and temperature is ranging from -25 °C to 110 °C, the output voltage is 895 mV, the temperature coefficient is 9.7 ppm/°C, the power consumption is 280.9 nW, and the PSRR is -41.7 dB. Under the same condition, the post-simulation results are as follow: the output voltage is 881 mV, the temperature coefficient is 33 ppm/°C, the power consumption is 239.5 nW, and the PSRR is -41 dB. Chen, Hsun-Hsiang 陳勛祥 2019 學位論文 ; thesis 32 zh-TW |
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碩士 === 國立彰化師範大學 === 電子工程學系 === 107 === This thesis presents a fully-MOSFET band-gap voltage reference circuit with low temperature coefficient. The circuit consists of a generator of PTAT, a generator of CTAT and a current source. The generator of PTAT utilize the self-cascade MOSFETs to generate the PTAT voltage, and the generator of CTAT is a MOSFET gate to source voltage, this voltage is a CTAT voltage when the MOSFET is operated in sub-threshold region.
We use TSMC 0.18 μm CMOS technology to design the circuit in this thesis. The pre-simulation results are when VDD is at 1.8 V and temperature is ranging from -25 °C to 110 °C, the output voltage is 895 mV, the temperature coefficient is 9.7 ppm/°C, the power consumption is 280.9 nW, and the PSRR is -41.7 dB. Under the same condition, the post-simulation results are as follow: the output voltage is 881 mV, the temperature coefficient is 33 ppm/°C, the power consumption is 239.5 nW, and the PSRR is -41 dB.
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author2 |
Chen, Hsun-Hsiang |
author_facet |
Chen, Hsun-Hsiang Wang, Wei-Shin 王惟昕 |
author |
Wang, Wei-Shin 王惟昕 |
spellingShingle |
Wang, Wei-Shin 王惟昕 Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture |
author_sort |
Wang, Wei-Shin |
title |
Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture |
title_short |
Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture |
title_full |
Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture |
title_fullStr |
Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture |
title_full_unstemmed |
Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture |
title_sort |
fully-mosfet bandgap voltage reference circuit with self-cascade architecture |
publishDate |
2019 |
url |
http://ndltd.ncl.edu.tw/handle/vhax89 |
work_keys_str_mv |
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