| Summary: | 碩士 === 國立彰化師範大學 === 資訊工程學系 === 107 === In the image processing research, the natural color image captured by the digital camera may be affected by insufficient lighting conditions, which causes the image brightness contrast to be compressed and cause some defects because we can use the fast dynamic range compression to preserve the regional image contrast. The algorithm in which the luminance part uses Gaussian filtering to obtain the regional average value for image smoothing, this algorithm can save the details of the image under dynamic range compression and preserve the original contrast.
The hardware implementation of this study uses fixed-point, unsigned numbers and displacements to improve computational efficiency, reduce the number of logic components, and the cost of hardware circuits. In addition, the use of look-up tables accelerates the processing of hardware processed signals. The speed and the pipeline structure enable each level to operate independently. Therefore, the pipelined architecture can effectively reduce the overall calculation time and circuit area. At the same time, we will study how to synchronize the elasticity. The principle and architecture of the circuit, and the application of the hardware design of this algorithm. Compared with the traditional pipeline circuit, the synchronous elastic circuit has the latency-insensitive feature, which allows the pipelined data path to be fully utilized by multiple threads.
The work completed in this paper consists of designing a flexible circuit with latency-insensitive properties and studying how to insert appropriate synchronous elastic control circuits into the image contrast algorithm circuit to support the operation of this algorithm and analyze how much circuit area and performance are sacrificed to achieve the function of the synchronous elastic circuit.
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