Physical Design for PPA with Mix-Cell Height

• Main Authors: Shao-Yang Ho, 何紹仰
• Other Authors: Yinyi Lin
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/twf484

碩士 === 國立中央大學 === 通訊工程學系在職專班 === 107 === For the semiconductor industry, the best solution for high efficiency and energy saving has been constantly researching. In essence, digital integrated circuits can greatly increase product competitiveness if they can reduce power consumption and maximize performance. In today's advanced semiconductor processes, standard-cell libraries can be developed with different cell heights, large cell heights (12T) provides higher driving power, but have larger area and power cost. The 7T cell has a small cell area but has weaker drive strengths and routing congestion and pin accessibility issues. Today's physical design methodology can use hierarchical methods to use standard cells of a particular height in a module, but cannot achieve a mixing height of standard cell implementation in a Traditional flatten physical design flow. On the other hand, reducing the clock power of the Clock Tree can effectively reduce the power consumption of the overall design. With the evolution of process and design methodology, multi-bits flip-flops have become one of the technologies to reduce clock area/power consumption. To achieve a balance between high performance and energy saving is an interesting and worthwhile question. Therefore, this paper proposes to use mixing high-standard cells implementation methodology with multi-bits flip-flops to reduce power and achieve the predetermined specifications. This paper uses TSMC's 28nm HPC+ process and uses OpenCores open source IP as the material to compare the difference and mathematical model of high-performance integrated circuit PPA at different frequencies.